The present invention relates to technology for improving reliability in a method of manufacturing a semiconductor device (or semiconductor integrated circuit).
Japanese Unexamined Patent Publication No. Hei 6 (1994)-174786 discloses a burn-in board with a grid conductor pattern in a test control circuit.
Japanese Unexamined Patent Publication No. Hei 10 (1998)-242608 discloses a four-layer wiring burn-in board in which two inner layers with blanket-type conductor patterns correspond to a power supply layer and a grounding layer.
Japanese Unexamined Patent Publication No. 2004-172647 and its equivalent U.S. Pat. No. 7,015,069 disclose a mesh conductor pattern as a pattern to reinforce a wiring substrate for the manufacture of FBGA (Fine-pitch Ball Grid Array).